Implementations relate to a method and device for compensating DC offset in RF transceivers. One or more particular implementations relate to a method for performing fine DC offset compensation.
Integrated direct conversion RF transceiver architectures became popular in the last decade for many different RF applications. They require a minimal set of building blocks, see FIG. 1. Each RX or TX signal path requires only one mixer with associated local oscillator which also simplifies the synthesizer. An IF filter is no longer needed.
But this architecture has also drawbacks. DC offset is introduced by the individual transceiver/receiver components like the amplifier, mixer, filter etc. It may distort the signal, and directly limits the available dynamic range. Strong offsets can saturate the signal path and also violate the digital signal processing. It became common to compensate this DC offset by adding DC voltages opposite to the occurring DC offset. Several different solutions have been developed in the past.
One typical approach is providing additional hardware blocks as disclosed in U.S. Pat. No. 6,756,924 B2 or U.S. Pat. No. 7,271,649 B2 or Tanaka, T. Yamawaki, K. Takikawa, N. Hayashi, I. Ohno, T. Wakuta, S. Takahashi, M. Kasahara, and B. Henshaw, “GSM/DCS1800 Dual Band Direct-Conversion Transceiver IC With a DC Offset Calibration System,” in 01 ESSCIRC Session 3.3, 2001. These blocks are typically dedicated to individual building blocks. The DC offset is measured and compensated. This approach requires additional elements not only for compensation, e.g. DACs, but also for measuring the DC offset and for determining the value needed for compensation. These blocks are running permanently. They increase the system complexity and consume additional power and space.
Other approaches determine the DC offset and the resulting DC compensation values permanently in the digital domain as disclosed in Marko Mailand and Hans-Joachim Jentschel, “Compensation of DC-Offsets and RF-Self-Mixing Products in Six-Port-Based Analog Direct Receivers,” in 14th IST Mobile & Wireless Communication Summit, Dresden, June 2005; or Russell Hoppenstein, “DC Offset Auto-Calibration of TRF371x,” Texas Instruments, 2010; or I.-H. Sohn, E-R. Jeong, and Y. H. Lee, “Data-Aided Approach to I/Q Mismatch and DC Offset Compensation in Communication Receivers,” IEEE COMMUNICATIONS LETTERS, vol. 6, no. 12, December 2002. The compensation values are introduced by a DAC in the analog section. But this concept prepares only one set of compensation values. This works well if the system gain is fixed. But systems with variable gain make the DC offset variably as well. Therefore, every new gain configuration requires new DC offset values to be measured and new compensation values to be set. This increases the acts to be done to change the gain as additional calibration acts must be executed as well for every new gain setting. Setting the gain as such becomes more complex and time consuming.
FIG. 1 shows a state-of-the art direct conversion receiver comprising a plurality of components like a low noise amplifier 12, mixer 13, filter 14, VGA 15, ADC 16, digital DC offset compensation 17 between radio frequency (RF) input 11 and baseband (BB) output. Direct conversion RF transceivers, e.g. for WLAN, did use more than one point to enter DC compensation voltages by additional DACs 18, 19. These DC compensation voltages (the calibration parameters) were typically determined from different measurements and from calculations in the digital domain, e.g. by a signal processor. It is common to add short cut and bypass switches to the individual transceiver/receiver components to measure the DC offset that occurs at each individual stage separately. Therefore, some of the components were operated under debug/test conditions (bypass or short cut mode) instead of the real operation conditions while the DC offset is measured. This introduces additional errors, e.g. due to different bias or temperature conditions, and increases the system complexity.
It is generally intended to find a set of calibration parameters that covers the complete gain control range. But this is not common in present implementations as the accuracy of the determined calibration parameters is insufficient. Therefore, the complete gain control range is split into several different sub ranges. Each different sub range has an own set of calibration parameters. Changing the gain from one sub range to another requires also the calibration parameters to be changed which is still complex and time consuming.
The transceiver (Rx path) with DC offset sources and compensation DACs (digital to analog converters) given in FIG. 1, can be simplified, see FIG. 2, to a set of variable gain stages 23 corresponding to mixer 13, 24 corresponding to filter 14, 25 corresponding to VGA 15 between RF input 21 and BB output 210, where the DC offset 211, 212, 213 and the compensation DACs 28 and 29 are connected to the input of each individual stage. The mathematical expression of this simplified model is given in FIG. 3 comprising a plurality of gain stages 321, . . . , 32k, . . . , 32n, DC offsets 330, 331, . . . , 33k, . . . 33n and compensation DACs 320, 321, . . . , 32k, . . . , 32n between RF input 31 and BB output 35.
The compensation DACs are connected to the signal path, FIG. 1. Each DAC adds a DC voltage that is opposite to the DC offset at this point so that the total DC becomes close to zero. This remaining voltage nonzero DC voltage becomes amplified by the gain stages that follow. As this gain is variable the resulting DC offset at the output of the signal path directly depends on the following total gain and the DC offset residual:mean(BBout(Atot,k))=Atok,k*(DCoff,k+DCcomp,k)The total gain for the gain stage k (k>0) is given by:
      A          tok      ,      k        =            ∏              j        =        1            k        ⁢                  ⁢          A              j        ,        i            Therefore, a good calibration method, procedure or algorithm should find values DCcomp,k that meet the relation:0≈DCoff,k+DCcomp,k The essential part of the calibration routines is therefore to determine DCoff,k accurately from different measured mean (BBout) values so thatDCcomp,k=−DCoff,k 
Throughout this document the following notations may be used:
number of total gain stages:
DC offset of gain stage k: DCoff,k 
DC compensation parameter of gain stage k: DCcomp,k 
DC offset residual of gain stage k: DCoff,k+DCcomp,k 
gain control range R of gain stage k: Ak,R 
gain i of stage k, were Ak, element of Ak,R: Ak,i 
total gain for gain stage k: Atot,k 
DC offset residual at ADC output (BB_out): DCres 